• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
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  • 优先权
    • 专利摘要:
    A thin film manufacturing method, wherein the thin film is an SOI wafer having an amorphous silicon layer, the method comprising: (1) providing a high resistivity silicon wafer, manufacturing a layer of silicon oxide and an amorphous silicon layer on its surface in this order after cleaning, the thickness of the silicon oxide layer being 150-300 A, the thickness of the layer amorphous silicon being 1-5 μm; (2) providing a low resistivity silicon wafer, fabricating a silicon oxide layer on its surface after cleaning, the thickness of the silicon oxide layer being 2000-10000 A; (3) implanting hydrogen ions onto the low resistivity silicon wafer provided with the silicon oxide layer fabricated in step (2) to cause hydrogen ions to penetrate the silicon oxide layer into the silicon wafer and reach the required depth, then cleaning with SPM, DHF, SC1 and SC2 in that order;
    公开号:FR3058257A1
    申请号:FR1758203
    申请日:2017-09-06
    公开日:2018-05-04
    发明作者:Wei Sun
    申请人:Shenyang Silicon Tech Co Ltd；
    IPC主号:
    专利说明:

    Holder (s): SHENYANG SILICON TECHNOLOGY CO., LTD. SN.
    Extension request (s)
    Agent (s): PAUL HERARD CONSEIL.
    FR 3 058 257 - A1 (04) PROCESS FOR THE MANUFACTURE OF THIN FILM.
    The invention relates to a method for manufacturing a thin layer, in which the thin layer is an SOI wafer provided with an amorphous silicon layer, the method comprising:
    (1) supply of a high resistivity silicon wafer, manufacture of a layer of silicon oxide and a layer of amorphous silicon on its surface in this order after cleaning, the thickness of the oxide layer silicon being 150-300 A, the thickness of the amorphous silicon layer being 1-5 gm;
    (2) supplying a low-resistivity silicon wafer, manufacturing a layer of silicon oxide on its surface after cleaning, the thickness of the layer of silicon oxide being 2000-10000 A;
    (3) implantation of hydrogen ions on the low resistivity silicon wafer provided with the layer of silicon oxide manufactured in step (2), so as to cause the hydrogen ions to penetrate the layer of silicon oxide into the silicon wafer and reach the required depth, then cleaning with SPM, DHF, SC1 and SC2 in this order;
    Thin film manufacturing process TECHNICAL AREA
    The present invention relates to the field of technology for manufacturing silicon on insulator (SOI) wafers, in particular to a process for manufacturing the thin layer, the manufactured layer being mainly used for an RF device.
    EXISTING TECHNOLOGY
    The materials currently used in the RF front modules are:
    1. SOQ (silicon on quartz), SOS (silicon on sapphire): SOQ is identical to conventional SOI, which generates a lower leakage current; due to its lower parasitic capacity, the performance of the circuit under high frequency is improved. The advantage of the SOS is its particularly good electrical insulation, which effectively prevents radiation caused by leakage currents from spreading to adjacent elements. Substrates such as SOQ and SOS can achieve excellent RF performance, but since this type of structure is very rare, these substrates are very expensive.
    2. High resistivity silicon substrates: their resistivity is greater than 500 ohms.cm. This type of substrate is less good than the first, it does not benefit from the structural advantages of the SOI type, but costs less.
    3. SOI substrate with high resistivity: this type of substrate has structural advantages, but its performance is less good than the first.
    One of the reasons for the formation of the low resistivity layer is that due to the existence of pollutants on the surface of the low resistivity layer before binding, these pollutants are packaged during the binding process in the interface of bond and can spread to the high resistivity substrate. Another reason for the formation of the low resistivity layer is the high content of oxygen atoms in the substrate; it is therefore necessary to carry out a heat treatment in order to precipitate the oxygen atoms to obtain the substrate with high resistivity. However, the diffusion of oxygen atoms and the heat treatment process cause the surface resistivity of the substrate thus formed to be low. It is currently difficult to master these two reasons.
    4. On the basis of point 3, the SOI substrate with high resistivity is improved by adding a layer having defects: a large number of techniques are tested for this purpose, but this has drawbacks: sensitivity to the manufacture of SOI and production heat during the following process of manufacturing integrated circuit components, difficulty in manufacturing materials having good thermal stability.
    SUMMARY OF THE INVENTION
    This invention aims to remedy the insufficiency of the existing technology concerning the supply of a process for manufacturing the thin layer, the thin layer designating the SOI wafer provided with a layer, the amorphous silicon layer being included in the SOI wafer, and the effective combination of amorphous silicon and silicon oxide which can effectively inhibit the parasitic conductivity of the surface of the silicon substrate, limit the variations in capacitance and reduce the harmonic power generated, so as to reduce the loss of resistivity of SOI substrate with high resistivity up to a minimum value.
    To this end, the technological diagrams used by the invention are as follows:
    A method for manufacturing a thin layer, namely a method for manufacturing an SOI wafer provided with an amorphous silicon layer, comprises the following steps:
    (1) supply of a high-resistivity silicon wafer (the resistivity of the silicon wafer is greater than 1000 ohms.cm), manufacture of a layer of silicon oxide and of a layer of amorphous silicon at its surface after cleaning in this order, the thickness of the silicon oxide layer being 150-300A, the thickness of the amorphous silicon layer being 1-5 µm; wherein the high resistivity silicon wafer is cleaned with DHF, SCI and SC2 in order to remove the natural oxide layer and pollutants on the surface of the silicon wafer; then manufacture of the silicon oxide layer on the surface of the high resistivity silicon wafer.
    The process for manufacturing the silicon oxide layer on the surface of the high resistivity silicon wafer is as follows: placing the high resistivity silicon wafer in the oxidation furnace, the oxidation temperature being 1060-1150 ° C, manufacture of the silicon oxide layer of the required thickness by controlling the oxidation time, then cleaning with SCI and SC2 in this order, in order to remove the pollutant present at the area.
    After the fabrication of the silicon oxide layer on the surface of the high resistivity silicon wafer, fabrication of the amorphous silicon layer on the surface of the silicon oxide layer, fabrication of the amorphous silicon layer is done by the LPCVD process (chemical vapor deposition under reduced pressure), in which the growth pressure is 0.1-5.0 Torr and the reaction temperature is 300 ° C-900 ° C; cleaning the high resistivity silicon wafer after manufacturing the amorphous silicon layer using SCI and SC2 in that order, in order to remove the impurities present on the surface.
    (2) supply of a low resistivity silicon wafer (the resistivity of the silicon wafer is less than 100 ohms.cm), manufacture of a layer of silicon oxide on its surface after cleaning, the thickness the silicon oxide layer being 200010000A; in which :
    the low resistivity silicon wafer is cleaned using DHF, SCI and SC2 in this order, in order to remove the natural oxidation layer and the pollutant on the surface of the silicon wafer, then the layer of silicon oxide is made on the surface of the low resistivity silicon wafer.
    The process for manufacturing the silicon oxide layer on the low resistivity silicon wafer is as follows: placing the low resistivity silicon wafer in the oxidation furnace, the oxidation temperature being 950-1020 ° C, control of the thickness of the silicon oxide layer obtained as a function of the oxidation time, then cleaning of the low resistivity silicon wafer provided with the silicon oxide layer manufactured by means of SCI and of SC2 in this order, in order to remove the pollutant present on the surface.
    (3) implantation of hydrogen ions on the low resistivity silicon wafer provided with the layer of silicon oxide manufactured in step (2), so as to cause the hydrogen ions to penetrate the layer of silicon oxide into the silicon wafer and reach the required depth, then cleaning with SPM, DHF, SCI and SC2 in this order;
    (4) bringing together the high resistivity silicon wafer from the treatment in step (1) and the low resistivity silicon wafer from the treatment in step (3) to form a whole by a bonding process, then carrying out an annealing treatment at a temperature of 200-450 ° C., after annealing, cleaning of the assembly after bonding using SCI and SC2 in this order;
    (5) separation of the assembly linked by step (4) using a microwave separation device, the separation temperature being less than 400 ° C., so as to obtain the SOI wafer with the amorphous layer;
    (6) cleaning of the SOI wafer provided with the amorphous layer obtained by separation, the cleaning being carried out by means of SPM, DHF, SCI and SC2 in this order, in order to remove the silicon slag and other pollutants present on the surface of the SOI; then performing an annealing treatment at a temperature between 1000-1500 ° C after cleaning;
    (7) cleaning the SOI wafer provided with the amorphous layer treated by the annealing of step (6) using DHF, in order to remove the oxidation layer produced by the annealing at high temperature, then use of SCI and SC2 in this order in order to eliminate chemical liquid pollutants and surface pollutants, followed, finally, by the execution of a CMP process to make the silicon of its upper layer reach the thickness required, i.e. to obtain the finished SOI wafer product with an amorphous layer conforming to the required specifications.
    The SOI wafer with the amorphous silicon layer produced in accordance with the invention has the following advantages:
    1. The technological advantage of the combination of amorphous silicon and silicon oxide lies in a high defect density. The application of the combined layer of amorphous silicon and silicon oxide effectively inhibits the parasitic conductivity of the surface of the silicon substrate, limits the variations in capacitance and reduces the harmonic power generated.
    2. The frozen carrier of the amorphous layer gives the silicon-based material a real high resistivity. Reduce the PSC (parasitic surface conduction) of the SOI substrate with high resistivity.
    3. The advantage of the amorphous silicon technology of the present invention lies in the high defect density; the application of the layer of amorphous silicon with high thermal stability is also compatible with the bonding process. Block the potential under the oxide layer, limit capacitance variations and reduce the harmonic power generated.
    4. The high resistivity SOI substrate with an amorphous layer reduces the RF loss of the substrate, the amorphous layer and the high resistivity silicon increase the linearity of the substrate, the high resistivity SOI substrate with the amorphous layer reduces the voltage DC polarization and is compatible with CMOS, and reduces RF loss.
    5. The present invention makes it possible to manufacture high quality components at a reduced manufacturing cost.
    SHORT DESCRIPTION OF THE FIGURES
    Fig. 1 is a process diagram according to the invention, in which: (a) high resistivity silicon wafer; (b) making a layer of silicon oxide; (c) making an amorphous silicon layer; (d) low resistivity silicon wafer; (e) manufacturing a low resistivity silicon wafer with a layer of silicon oxide; (f) implantation of hydrogen ions; (g) binding; (h) microwave separation.
    DETAILED DESCRIPTION
    The following is a detailed description of certain exemplary embodiments of the present invention with reference to the appended figures.
    Embodiment 1
    The present embodiment provides a method for manufacturing a thin layer, in which the thin layer is an SOI wafer provided with an amorphous silicon layer and the manufacture comprises the steps below:
    1. Provide a high resistivity silicon wafer, the resistivity of which is greater than 1000 ohms.cm, and clean its surface with DHF, SCI and SC2 in order to remove the oxidation layer natural and the pollutant present on the surface of the silicon wafer; use the test device to test the state of the particles on the surface of the silicon wafer, the silicon wafers meeting the requirement will come into play in the next step (FIG. 1 (a)) ·
    2. Refer to FIG. l (b), fabricating a layer of silicon oxide on the surface of the high resistivity silicon wafer, the thickness of the oxide layer formed being about 200 A; the manufacturing process is as follows: place the high resistivity silicon wafer in the oxidation furnace, the oxidation temperature being approximately 1100 ° C, then clean using SCI and SC2 in this order, in order remove the pollutant from the surface. Use the test device to test the condition of the particles on the surface of the silicon wafer, use the test device to test the thickness of the silicon oxide and other parameters (such as particles of the silicon oxide layer, electrical parameters). The silicon wafers that meet the requirement will come into play in the next step.
    3. Referring to FIG. l (b), by the LPCVD process (chemical vapor deposition under reduced pressure), in which the growth pressure is 0.1-5.0 Torr and the reaction temperature is 300-900 ° C, fabricating the amorphous silicon layer on the silicon oxide layer (FIG. 1 (c)), the thickness of the amorphous silicon layer being 1-5 µm; the high resistivity silicon wafer after fabrication of the amorphous silicon layer is cleaned using SCI and SC2 in this order to remove impurities from the surface. Use the testing device to test the thickness of the amorphous silicon produced. Silicon wafers with a thickness within the above range will be taken into account in the next step.
    4. Provide a low resistivity silicon wafer (the resistivity is less than 100 ohms.cm), clean with DHF, SCI and SC2 in this order, in order to remove the natural oxidation layer and the pollutant present on the surface of the silicon wafer (FIG. l (d)). Use the test device to test the admissibility of the particles present on the surface and the state of the geometric parameters, select the admissible plates to carry out the next step.
    5. Fabricate the silicon oxide layer on the low resistivity silicon wafer from step (4), the manufacturing process is as follows: place the low resistivity silicon wafer in the oxidation furnace, oxidation temperature being about 1000 ° C; clean the low resistivity silicon wafer with the silicon oxide layer fabricated using SCI and SC2 in that order, to remove the pollutant from the surface (FIG. l (e)). Use the testing device to test the thickness of the oxide layer and the surface condition of the silicon wafers obtained, select the appropriate silicon wafer to carry out the next step.
    6. Proceed with the implantation of hydrogen ions in the low-resistivity silicon wafer provided with the silicon oxide layer manufactured in step (5), to ensure that the hydrogen ions penetrate the layer of silicon oxide into the silicon wafer and reach the required depth (fig. l (f)), then clean using SPM, DHF, SCI and SC2 in this order. Test the silicon wafers, select the eligible silicon wafers to carry out the next step.
    7. Combine the high resistivity silicon wafer obtained in step (3) and the low resistivity silicon wafer obtained in step (6) to form a whole by bonding, then perform an annealing treatment at low temperature. ; the annealing temperature is 200-450 ° C. Increase the bonding strength between the plates by annealing (FIG. L (g)); then run a SONOSCAN D9600 ™ C-SAM test, a SONOSCAN D9600 ™ C-SAM test, after the tests, clean using SCI and SC2 in this order. Select eligible silicon wafers with no holes after bonding to perform the next step.
    8. Separate the assembly linked by step (7) using a microwave separation device, the separation temperature being less than 400 ° C., so as to obtain the SOI wafer provided with the amorphous layer (fig. l (h)). The inverted silicon can be reused after separation (the silicon wafer whose thickness does not meet the requirement will be eliminated). The microwave separation device is a device disclosed in Chinese patent application No. 201220360782.6 entitled "microwave cracking equipment".
    9. Clean the SOI wafer with the amorphous layer obtained by separation using SPM, DHF, SCI and SC2 in this order, in order to remove the silicon slag and other pollutants present on the surface of the Self. Run the layer thickness test (which tests the thickness of the top layer of silicon), select the admissible SOI to execute the next step.
    10. Perform a high temperature annealing on the wafer
    SOI with the amorphous layer after cleaning, the annealing temperature being 1000-1500 ° C, in order to eliminate pitting damage, repair the network.
    11. Use DHF to clean the SOI wafer with the amorphous layer treated in step (10), in order to remove the oxidation layer produced by high temperature annealing, then use the SCI and SC2 to eliminate chemical liquid pollutants and surface pollutants.
    12. Carry out the CMP process on the SOI wafer provided with the amorphous layer treated by step (11), so that the silicon in the upper layer reaches the required thickness. Then perform different tests (eg surface metals, particles, geometric parameters, resistivity, layer thickness, hardness, etc.).
    权利要求:
    Claims (9)
    [1" id="c-fr-0001]
    Claims
    1. Method for manufacturing a thin layer, in which the thin layer is an SOI wafer provided with an amorphous silicon layer, the manufacturing method comprising the following steps:
    (1) supply of a high resistivity silicon wafer, manufacture of a layer of silicon oxide and a layer of amorphous silicon on its surface in this order after cleaning, the thickness of the oxide layer of silicon being 150-300 A, the thickness of the amorphous silicon layer being 1-5 µm;
    [2" id="c-fr-0002]
    (2) supply of a low resistivity silicon wafer, manufacture of a layer of silicon oxide on its surface after cleaning, the thickness of the layer of silicon oxide being 200010000 A;
    [3" id="c-fr-0003]
    (3) implantation of hydrogen ions on the low resistivity silicon wafer provided with the layer of silicon oxide manufactured in step (2), so as to cause the hydrogen ions to penetrate the layer of silicon oxide into the silicon wafer and reach the required depth, then cleaning with SPM, DHF, SCI and SC2 in this order;
    [4" id="c-fr-0004]
    (4) joining of the high resistivity silicon wafer obtained in step (1) and the low resistivity silicon wafer obtained in step (3) to form a whole by a bonding process, then execution of an annealing treatment at a temperature of 200-450 ° C., after annealing, cleaning of the assembly after bonding using SCI and SC2 in this order;
    [5" id="c-fr-0005]
    (5) separation of the assembly linked by step (4) using a microwave separation device, the separation temperature being less than 400 ° C., so as to obtain the SOI wafer with the amorphous layer;
    [6" id="c-fr-0006]
    (6) cleaning the SOI wafer provided with the amorphous layer obtained by separation, then carrying out an annealing treatment at a temperature of 1000-1500 ° C; and (7) cleaning the SOI wafer provided with the amorphous layer treated by the annealing of step (6) using DHF, in order to remove the oxidation layer produced by the annealing at high temperature, then use SCI and SC2 in this order in order to eliminate chemical liquid pollutants and surface pollutants, followed, finally, by the execution of a CMP process to ensure that the silicon of its upper layer reaches l required thickness, that is to say to obtain the finished SOI wafer product with an amorphous layer conforming to the required specifications.
    2. A method of manufacturing a thin film according to claim 1, in which, in step (1), the high resistivity silicon wafer designates the silicon wafer whose resistivity is greater than 1000 ohms.cm.
    3. A method of manufacturing a thin film according to claim 1, comprising, in step (1), cleaning the high resistivity silicon wafer using DHF, SCI and SC2 in this order, in order to removing the natural oxidation layer and the pollutant on the surface of the silicon wafer, then manufacturing the silicon oxide layer on the surface of the high resistivity silicon wafer.
    4. A method of manufacturing a thin film according to claim 1, wherein, in step (1), the method of manufacturing the layer of silicon oxide on the surface of the high resistivity silicon wafer is as follows: : placing the high resistivity silicon wafer in the oxidation furnace, the oxidation temperature being 1060-1150 ° C, manufacturing the silicon oxide layer of the required thickness by controlling the time of oxidation, then cleaning with SCI and SC2 in this order to remove the pollutant present on the surface.
    5. A method of manufacturing a thin film according to claim 1, wherein, in step (1), after the manufacture of the silicon oxide layer on the surface of the high resistivity silicon wafer and the manufacture of the amorphous silicon layer on the surface of the silicon oxide layer, the manufacturing of the amorphous silicon layer is done by the LPCVD process (chemical vapor deposition under reduced pressure), in which the growth pressure is 0.1-5.0 Torr and the reaction temperature is 300 ° C-900 ° C; cleaning the high resistivity silicon wafer after manufacturing the amorphous silicon layer using SCI and SC2 in that order, in order to remove the impurities present on the surface.
    6. A method of manufacturing a thin film according to claim 1, in which, in step (2), the low-resistivity silicon wafer designates the silicon wafer whose resistivity is less than 100 ohms.cm.
    [0007]
    7. A method of manufacturing a thin film according to claim 1, comprising, in step (2), cleaning the low-resistivity silicon wafer using DHF, SCI and SC2 in this order, in order to eliminating the natural oxidation layer and the pollutant on the surface of the silicon wafer, then manufacturing the silicon oxide layer on the surface of the low resistivity silicon wafer.
    [0008]
    8. A method of manufacturing a thin film according to claim 1, wherein, in step (2), the method of manufacturing the layer of silicon oxide on the low resistivity silicon wafer is as follows: placement of the low-resistivity silicon wafer in the oxidation furnace, the oxidation temperature being 950-1020 ° C., control of the thickness of the layer of silicon oxide obtained as a function of the oxidation time, then cleaning of the low resistivity silicon wafer provided with the silicon oxide layer manufactured using SCI and SC2 in this order, in order to remove the pollutant present on the surface.
    [0009]
    9. A method of manufacturing a thin layer according to claim 1, in which, in step (6), the method of cleaning the SOI wafer provided with the amorphous layers obtained by separation is carried out by means of SPM, DHF, of SCI and SC2 in this order, in order to remove the silicon slag and other pollutants present on the surface of the SOI.
    HR-Si
    If (cl)
    HF-- s (b) 1
    Amorphous silicon
    MF -U c)!
    I | i
    HP- a ^ β1 · ΒΒΐ!
    Amorphous silicon iii
    HP- i
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    法律状态:
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